世界末日英文行业词汇英文缩写

2021年1月11日发(作者：姜俊平)
Glossary of Acronyms Relevant to Electronics M anufacturing
ACI
ANSI
AOI
ASIC
ASM< br>ASTE
ASTM
ASQC
ATE
ATG
BGA
CA D
CBGA/CCGA
CFC
CMA
CMOS
CMT
Aut omatic Component Insertion
American National Standards Institute
Automated Optical Inspection. Test fixture method in which printed circuit boards
are checked at bare-board, pre- or post-soldered stages of assembly by optical
means.
Application Specific Integrated Circuit
American Society of Metals
American Society Test Engineers
American Society for Testing and Materials
American Society Quality Control
Automatic Test Equipment. Equipment designed to automatically analyze
functional or static parameters in order to evaluate performance degradation. It
may also be designed to perform fault isolation.
Automatic Test Generation. Computer generation of a test program based solely
on the circuit technology, requiring little or no manual programming effort.
Ball Grid Array. A component whose terminations are on the bottom of the
package, and are in the shape of solder balls and in a grid array pattern. This
generally covers components that have them in a full array or in a partial array
with “missing” balls in the center.
Computer Aided Design. A computer based system to assist designers in the
design, topological layout and drawing of an electronic component, assembly, or
system.
Ceramic Ball Grid Array/Ceramic Column Grid Array. A grid array packaged
component that has ceramic as the substrate of the package, and may have
either solder balls or solder columns for connections.
Chlorinated Fluorocarbon.
Circuit Mil Area. A unit of area equal to the area of a circle whose diameter is
one mil (0.001”). Used chiefly in specifying cross-sectional areas of conductors.
Complementary Metal Oxide Semiconductor
Chip Mount Technology. Any packaging or electronic assembly manufacturing
technology, such as TOB, COB, or flip chip, that connects bare (unpackaged) IC
chips to the substrate.
COBChip-on-Board. A situation where the silicon IC chip is mounted directly to the
electronic assembly substrate or PWB without an intermediate packaging step.
Connections between the chip and the board are generally made with bond wired
(also sometime called chip and wire), but the terminology is occasionally used for
any chip connection technique such as flip chip (solderable bumps or tape
automated bonding.
Chip Scale Package. Active, multi-I/O package that is no larger than 125% of the
size of the silicon IC.
Coefficient of Thermal Expansion. See TCE
Design for Manufacturability
Design for Test
Dual In-Line. Component shape with two parallel rows of connection leads.
Dual In-Line Package. A popular through hole package with leads in rows on
opposite sides of the package.
Dynamic RAM. Read-write memory that must be refreshed (read or written into)
periodically to maintain the storage of information.
Device Under Test. Component, PCB, or assembly subjected to a test. Also
known as unit under test (UUT) and loaded board.
Electronic Industries Association in Japan
Electrostatic Discharge. A transfer of electrostatic charge between bodies at
different electrostatic potentials caused by direct contact or induced by an
electrostatic field.
Environmental Stress Screening. Manufacturing stage in which all assemblies
are subjected to abnormal stresses, with the aim of forcing all early failures to
occur. Also known as reliability testing.
Flip Chip Attach. The technique of attachment of an IC chip to a substrate using
solderable bumps between the silicon chip and substrate.
Fine Pitch Technology. The portion of surface mount technology that included
components that typically have lead pitch, or center-to-center spacing, between
0.4mm and 0.8mm.
Flat Pack. A low profile IC package, which typically has gull wing type of leads
on two or four sides.
The most commonly used epoxy-fiberglass material standard for printed circuit
boards. The “FR” refers to flame retardant.
Hot Air Soldered Leveled. Hot air is used to blow off the excess after the PWB is
dipped in solder. Typically used with the SMOBC process.
Integrated Circuit. A small, complete circuit made by vacuum deposition and
other techniques, usually on a silicon chip, and mounted in a package.
CSP
CTE
DFM
DFT
DIL
DIP
DRAM
DUT
EIAJ
ESD
ESS
FCA
FPT
FP
FR-4
HASL
IC
IEEE
ILB
IMAPS
IMC
Insti tute of Electrical and Electronics Engineers
Inner Lead Bonding. Process of bonding termination, which leads to a tape
automated bond integrated circuit’s bumps.
International Microelectronics and Packaging Society.
Intermetallic Compound. Metallic compounds that form at the interfaces between
different metals, such as copper-tin compounds that form at the interface of a
solder joint and a copper lead. IMCs typically have significantly different
properties, such as tensile strength.
Institute for Interconnecting and Packaging Electronic Circuits
Infrared. Soldering process that uses infrared energy as the primary method of
heating.
International Standards Organization.
Joint Electronic Devices Engineering Council, a part of the Electronic Industries
Association (EIA) that publishes specifications and standards for electronic
components.
Known Good Board. A correctly operating PCB. It is used in learning or
debugging a test program in development and for comparison testers where it
serves as the standard unit by which other PCBs are compared.
Known Good Die
Leadless Ceramic Chip Carrier (or CLCC for Ceramic Leadless Chip Carrier). A
hermetically sealed ceramic package that has pads (castellations) around its
sides for solder connection in a surface mounting application.
Leaded Ceramic Chip Carrier. A hermetically sealed ceramic package that has
leads around its sided for solder connection in a surface mounting application.
Typically, thee packages have over 28 leads.
Large Scale Integration. Arrays of ICs on a single substrate that comprise 100 or
more individual active circuit functions or gates.
Multichip Module. A circuit comprised of two or more silicon devices bonded
directly to a substrate by wire bond, TAB, of flip chip.
Metal Electrode Face Bonding. A cylindrical leadless component with a round
body and metals terminals on the ends.
Mutli Layer Board. A PWB that has more than two conductor layers. The layers
are interconnected by the plated-through holes.
Moisture Sensitive Device.
Mean Time Between Failures. The arithmetic or statistical mean average time
interval, usually in hours, that may be expected between failures of an operating
unit. Results should be designated actual, predicted, or calculated.
Mean Time To Failure. Average time between failures.
IPC
IR
ISO
JEDEC
KGB
KGD
LCCC
LDCC< br>LSI
MCM
MELF
MLB
MSD
MTBF
MTT F