material什么意思半导体英文名词解释

2021年1月19日发(作者：april是什么意思)
名词解释
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英文版

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半导体技术天地

AFM

Atomic Force Microscope: AFM is a non-destructive surface topography analysis technique that
provides surface topographic image with a resolution in order of angstroms. A very sharp silicon
tip with a radius in the order of ~10A is scanned close to the sample surface to get surface
topology. AFM is a powerful tool to investigate surface roughness of silicon wafer under the gate
dielectric.

ALD

Atomic Layer Deposition: Closely related to conventional CVD, ALD is a thin film deposition
technique that deposits very thin films with an excellent film uniformity and conformality. Single
crystal semiconductor films such as Si, Ge and GaAS, metallic films such as tungsten and copper,
and dielectric films such as oxides and nitrides can be deposited with ALD. Also known as
ALCVD.
APCVD

Atmospheric- pressure Chemical Vapor Deposition (see also CVD).
APM

A mixture of Ammonia hydroxide, hydrogen Peroxide and water used for cleaning wafer surface
primarily to remove organic particles.

ARC

Anti-reflective Coating: a thin layer of dielectric film, such as SiN, coated over the wafer surface
to improve lithography resolution by reducing light scatter from the wafer surface

ArF
ArF is a source of an excimer laser that produces high power laser at a wavelength of 193nm.

ASIC
Application Specific Integrated Circuits: As opposed to general purpose IC’s, ASIC is designed
and produced for a certain specific application. Also known as custom IC’s.

BEOL

Back End of the Line: BEOL typically refers to processing steps that involve ILD deposition,
contacts and metal interconnects. See FEOL.

BiCMOS
BiCMOS refers to circuits and process technology that offer both bipolar junction transistors (BJT)
and CMOS transistors on the same chip. BiCMOS combines high current driving capability of
BJT and low power consumption of CMOS. BJT is typically used to drive a large capacitive load
while CMOS transistors are used to perform logic functions. BiCMOS technology is more
complex and more expensive than CMOS technology, and typically serves niche markets.

Bird’s Beak

During LOCOS (local oxidation of silicon) oxidation, two-dimensional oxidation occurs at the
edge of field oxide. As a result, oxidation extends into the active area at the surface underneath the
silicon nitride, forming a bird’s

beak. Because of bird’s beak, the effective area of the active
region is reduced. In the bird’s beak region of gate oxide, oxide thinning can occur due to Kooi
effect (also known as “white ribbon” effect). See Kooi effect.

BJT
Bipolar Junction Transistor: BJT has three parts; collector, base and emitter. In a vertical BJT, the
emitter is the most heavily doped region and the collector the least heavily doped. “Bipolar” refers
to the fact that two types of charge carriers (electron and hole) contribute to the current flow, one
being the majority carrier and the other the minority carrier. In an NPN BJT, electron is the
majority carrier. In a PNP BJT, hole is the majority carrier. In contrast, MOSFET is a “unipolar”
device in the sense that only one type of charge carrier is responsible for the current flow (See
MOSFET). BJT is characterized by high current gain and high switching speed. However, its large
transistor size and high power consumption limit its use in very large scale integration. BJT
transistor effect was first discovered by three Bell Labs researchers in 1947. This discovery led
them to winning the Nobel Prize in physics in 1956. To learn more about the history of transistors,
visit the following site.

BMD
Barrier Metal Deposition: Barrier metal is a thin metallic film deposited in cotacts, via and under
the metal interconnects. The purpose of barrier metal is to prevent tungsten from reacting with
material underneath during contact fill process or to serve as a diffusion barrier to Cu
interconnects. TiN, TiW and TaN are the typical barrier material.

BOE

Buffered Oxide Etch: Silicon dioxide etching solution made of a mixture of NH4F, HF and H2O.

BPSG

Borophosphosilicate Glass: BPSG oxide is typically used in the back end of the flow in the
semiconductor process to passivate the surface and to provide smooth topology. The oxide is
doped with boron and phosphorus, which gives BPSG a gettering capability of sodium or metallic
mobile ions, and allows it to flow at a lower temperature.
BPTEOS

Borophosphosilicatetetraethylorthosilicate: BPTEOS is a BPSG film produced using TEOS
instead of silane (SiH4) that is used in a more conventional BPSG film. BPTEOS produces
void-free dense film (see also TEOS).

HBSIM

Berkeley Short-channel IGFET Model: BSIM is a MOSFET model developed by researchers at
EE department of University of California, Berkeley for MOSFET circuit simulation. BSIM is one
of the most widely used device models for circuit simulation today.

BST

Barium Strontium Titanate (BaSr)TiO3: a high k dielectric material with dielectric constant in the
range of 160-600 used in DRAM storage capacitors.

BTS

KBiased Thermal Stress: BTS is one of the important techniques to evaluate the reliability of
dielectric film. In a BTS test, an oxide capacitor is put under an accelerated voltage stress at a high
temperature and electrical parameters, such as flat band voltage, are measured as stress progresses.

CCD
Charge Coupled Device: CCD uses a packet of charge (electrons or holes) that is transferred along
the surface of semiconductor underneath the electrodes under control of clock signals. Signal
processing is performed during charge transfer or at the output. Imaging is one of the most
important applications of CCD, such as image sensor in the video cameras.

CD

Critical Dimension: CD is the feature size defined by lithography or etch process. Usually, it
refers to the minimum feature size for a particular layer in semiconductor processing. Feature size
defined by litho process is commonly called DICD, and the final feature size after etch is
commonly called FICD.

CMOS

Complementary MOS: CMOS refers to circuits and process technology that provide both P-ch and
N-ch MOSFET on the same chip. In CMOS circuits, P-ch MOSFET acts as an active load and
N-ch MOSFET acts as a pull- down driver. In a steady state, CMOS circuits consume extremely
low DC power because there is no DC current path from the power supply (Vcc) to the ground
(Vss), making CMOS an ideal candidate for a large scale integration. In CMOS technology, P-ch
MOSFETs are formed in N-well and N-ch MOSFETs in P-
well. This is called “twin
-
well” CMOS
technology. CMOS technology has become the mainstream technology in today’s IC industry for
most of logic and memory products (see Technology section of this Web site).

CMP

Chemical Mechanical Polishing (or Planarization): CMP is a semiconductor fabrication process to
planarize wafer surface. Wafer surface is grinded by a rotating disc with chemical slurries aiding
polishing process. Metals such as tungsten, aluminum, copper, and dieletrics such as oxide, and
poly-
silicon are polished by CMP. In today’s advanced CMOS process, CMP is used to planarize
the surface after STI trench fill and for ILD planarization after metal interconnect gap fill.

COP

Crystal Originated Pits: COP is caused mainly by voids at the wafer surface. While epitaxial
wafers are COP free, COP is common with non-epitaxial silicon wafers. COP can have a negative
impact on gate oxide integrity. Argon-annealing of wafers have shown a significant reduction of
COP.

CVD

Chemical Vapor Deposition is a technique to deposit thin films on a silicon wafer. In a CVD
process, two or more gaseous materials go through a chemical reaction in a CVD reactor chamber.
As a result of chemical reaction, dielectric molecules form and subsequently are deposited on the
wafer surface. Common dielectric films deposited by CVD are SiO2, Si3N4, SiON. Many
different types of CVD technique are available today, based on reactor type, and process
conditions, such as pressure and plasma. These include LPCVD, APCVD, PECVD, HDPCVD and
MOCVD.

Denuded Zone

Denuded zone is a thin layer of silicon at the top surface of a wafer that is free of defects and
contaminants. It is created after a wafer goes through a “gettering” process. Denuded zone is
where the semiconductor devices are formed.

DHF

Diluted HF: HF diluted in water typically with a ratio of 100:1 (H2O:HF)
DIBL

Drain-induced Barrier Lowering: In a short-channel MOSFET, the potential barrier between the
source and drain is lowered when drain electric field is high and penetrates toward the source.
This effect is called DIBL. DIBL increases off-state leakage current and causes drain-to-source
punch-through. DIBL is one of the main limiting factors in the scaling of short- channel transistors.
DLTS

Deep Level Transient Spectroscopy: Deep level transient spectroscopy measures deep trap levels
in semiconductors. The method is based on the capacitance change of a reverse biased diode when
deep levels emit their carriers after they are charged by forward bias pulse.

DMOS

Double-diffused MOS: In N-ch DMOS, channel length is determined by the difference in
diffusivity of p-type dopant that forms the channel and n-type dopant that forms the source. The
region outside the p-type channel is an n-type drift region. In DMOS, a short channel length can
be achieved with a relatively long gate length.

Dual-Gate CMOS (also see CMOS)

In today’s advanced CMOS technology, gate poly
-silicon for N-ch and P-ch MOSFET is doped in
n+ and p+, respectively. This is called dual-gate CMOS. In dual-gate CMOS technology, both
N-ch and P-ch transistors operate in a surface channel mode. Surface-channel transistors are less
prone to punch-through, and are easier to scale than the buried-channel transistors.

DRAM

Dynamic Random Access Memory: a charge storage capacitor and an access transistor comprise a
DRAM cell. Data is stored in the storage capacitor and is accessed through the access transistor,
which is typically an N-ch MOSFET. DRAM cell needs a periodic refreshing to keep the data
from being lost due to leakage. Data stored in DRAM is lost when power goes off. Two main
types of storage capacitors used in the industry are stacked capacitor and trench capacitor.

DUV

Deep Ultraviolet Lithography: DUV refers to a lithography generation that uses DUV light with
wavelength of 248nm. DUV light is obtained from KrFexcimer laser. The name DUV is used to
distinguish it from other generations; i-line with wavelength of 356nm, g-line with wavelength of
436nm or future generation of 193nm and 157nm.

EOT

Equivalent Oxide Thickness: For high k dielectric, or staked gate oxide, its electrical thickness is
converted to the equivalent SiO2 thickness for comparison purposes between different materials.

EPROM

Erasable Programmable Read Only Memory: In an EPROM memory cell, programming is done
electrically by hot carrier injection. Electrons generated by impact ionization tunnel through the
tunnel oxide, then are trapped in the floating gate poly-silicon. Erase is performed with shining
ultraviolet light on the memory chip, which clears trapped electrons out of the floating gate.

EEPROM

Electrically Erasable Programmable Read Only Memory: In EEPROM, erase is performed
electrically byte-by-byte on chip. This electrical erase capability is convenient but the memory cell
size is larger than EPROM, and as a result, EEPROM memory has lower density and higher price
than EPROM.

ELSI

Extremely Large Scale Integration: A term used to indicate the level of integration. ELSI refers to
a higher level of integration than ULSI. Below ULSI, in a descending order, follow VLSI, LSI,
MSI and SSI.

EM

Electro-Migration: Current flow in metal interconnects such as aluminum and copper creates
momentum transfer from electron to aluminum or to copper atoms. This causes metal atoms to
migrate in the direction opposite to current flow, resulting in an increase in metal resistance. In an
extreme situation, voids can form in the metal interconnects as a result of EM. EM is a serious
reliability issue for metal interconnects.

EOS

Electrical Overstress: refers to an electrical stress on semiconductor devices on a chip that is over
the electrical specification limit. Electrical signal overshoots in the input or output pins and ESD
(electrostatic discharge) are common examples of EOS.

EBL

Electron Beam Lithography: a maskless lithography using electron beams to pattern photoresist.

EPL

Electron-beam Projection Lithography

ESD

Electrostatic Discharge: When electrostatic charge stored on the human body or machine tools is
discharged through a semiconductor chip, it can create damages to the circuits and devices on the
chip. This is called ESD damage. Input and output pins of IC chips are vulnerable to ESD
damages. Robustness of semiconductor chip against ESD damage is evaluated using test methods
based on several ESD models; human body model, charged device model and machine tool model.

ESL

Etch Stop Layer: typically a thin SiN film, ESL film is deposited on the wafer after the silicidation
process of source, drain and gate poly is complete. ESL provides necessary etch selectivity during
subsequent contact etch process.

EUV

Extreme Ultraviolet Lithography; EUV is one of the next generation lithography (NGL) candidate
technologies. EUV uses a light with wavelength of around 10nm-20nm. EUV LLC is an US
industry-government consortium that carries out EUV research.

FAMOS

Floating-gate Avalanche MOS: refers to a non-volatile memory cell structure, where electrons are
generated by drain avalanche breakdown, then get trapped in the floating gate.

FEOL

Front-end of the line: usually refers to process steps from wafer start to completion of transistor
formation prior to first ILD deposition.

Flash Memory

A type of nonvolatile memory where charge is stored in the floating gate or at the oxide-nitride
interface. Data is preserved even when the power is off. For details, click
Nonvolatile section.

FRAM

Ferro-electric Random Access Memory

FTIR

Fourier Transform Infrared Spectroscopy: FTIR detects impurity levels in materials used in
semiconductor processing. Infrared spectroscopy is based on transmission and absorption
characteristic of excited electrons from impurities in the sample material. With Fourier
transformation of signals, a high sensitivity in impurity detection is achieved.

GIDL