SRIO协议解析

Serial RapidIO

协议解析

1.

物理层特性

1.1

Two transmitters(short run and long run) and a single receiver are specified for each of

three baudrates, 1.25, 2.50, and 3.125 GBaud.

1.2

The short run transmitter should be used mainly for chip-to-chip connections on either

the same printed circuit board or across a single connector.

1.3

The long run transmitter specifications use larger voltage swings that are capable of

driving

signals

across

backplanes.

This

allows

a

user

to

drive

signals

across

two

connectors and a backplane.

1.4

The most common equalization techniques that can be used

?

Pre-emphasis on the transmitter

?

A passive high pass filter network placed at the receiver. This is often referred to as

passive equalization.

?

The

use

of

active

circuits

in

the

receiver.

This

is

often

referred

to

as

adaptive

equalization.

2.

信号定义

Signal pin descriptions for a RapidIO 1x/4x LP-Serial port. The interface is defined either as

a

single-

or

four- lane,

full

duplex,

point-to-point

interface

using

differential

signaling.

A

single-lane

implementation

consists

of

4

wires

and

a

four-lane

implementation

consists

of

16

wires.

3.

Electrical Specifications

3.1

Short Run Transmitter Specifications

2.5 GBaud

、

3.125 GBaud

特性与

1.25GBaud

Short Run Transmitter AC Timing Specifications

基本相同，区别在于：

2.5 GBaud UI 400ps

3.125 GBaud UI 320ps

3.2

Long Run Transmitter Specifications

2.5 GBaud

、

3.125 GBaud

特性与

1.25GBaud

Long Run Transmitter AC Timing Specifications

基本相同，区别在于：

2.5 GBaud UI 400ps

3.125 GBaud UI 320ps

3.3

Receiver Specifications

2.5 GBaud

、

3.125 GBaud

特性与

1.25GBaud

Receiver Specifications

基本相同，区别在于：

2.5 GBaud UI 400ps

3.125 GBaud UI 320ps